Digital Signal Processing (DSP) systems that perform a specific and continuous processing task are often implemented in FPGA or ASIC technology. Beyond defining the algorithms and functions to be performed, the designer must also select how the numbers in the system are represented. Floating–point representation allows for very large and very small numbers and leaves a lot of freedom for the designer. But if we implement fixed–point arithmetic, the calculations will typically be performed faster using less logic and power resources. A fixed-point format is therefore often selected for DSP applications in FPGA and ASIC. Integer representation can be considered a special case of fixed-point representation and is also commonly used.
A high-level simulation model will typically contain floating-point numbers representing some physical property. This can for example be a voltage measured in volt (V). Coefficients and factors with a specific unit are also used, for example a bandwidth measured in hertz (Hz). A floating-point model can represent these values directly and we keep the units in the model.
When we arrive at a fixed-point or integer implementation there will be some relation between the numeric values and the physical properties they represent. The designer must retain control and understanding of these relationships throughout the design. The implemented values will also have a finite range, and this range must support the required functionality. The figure below shows a simplified example of how a voltage might be represented as a 4-bit unsigned in implementation.
It is also essential to maintain control of signal scaling as it evolves throughout the data path. There can be cases where we first represent an angle in degree units, but then must change to radians. This numerical change must be handled appropriately. In other cases, we may change a value represented in volts (V) to millivolts (mV) or apply some other scaling factor.
Whenever coefficients are numerically very small, may also be appropriate. A large portion of the numeric range used for the numbers in the data path following this coefficient may be unused unless we take specific measures. By scaling the numeric range, we can compensate for this and optimize the number of bits used at any given point. The designer must monitor this scaling and ensure that the results are presented at the correct scale.
The figure below shows how the number of bits used to represent a parameter must be increased when two numbers with the same format are multiplied. In this example, two 4-bit numbers are multiplied, and 8 bits must be used to represent the full range of the result. The dashed line shows the division between the bits used to represent the integer and the fractional part. With fixed-point format, both parts of the number grow and the tools handle this for us.
With integer multiplication, the resulting numeric value is always numerically larger than the inputs, unless one input is 0 or 1. This usually necessitates scaling of the results, which must be done manually.
Number of bits
To truly optimize a DSP system for logic complexity and power, the number of bits used to represent the values must be considered throughout the design. Following multiplications, as seen in the example above, a reduction in the output bit width is often performed.
This consideration applies to all number formats. Limiting the number of bits involves truncation and rounding, which has a variety of consequences, including quantization . To optimize system performance, the designer should keep a budget of these effects.
We have seen that the choice of number formats is an important part of a DSP design, even if it’s not directly a part of the algorithms. The number format, number of bits, and location of radix points must be controlled, and the designer must fully comprehend what the numbers represent. This ensures correct functionality and affects performance, logic resource use, and power.