Live online course: ‘Advanced VHDL Verification – Made simple’​ – using UVVM

A general introduction to modern verification methodology and to UVVM – the world-wide #1 FPGA verification methodology, and also the fastest growing verification methodology independent of HDL.

Efficiency and quality is all a question of overview, readability, extensibility, maintainability and reuse, – and a good architecture is the answer. This applies for both Design and Verification 

On average half the development time for an FPGA is spent on verification. It is possible to significantly reduce this time, and major reductions can be accomplished with minor adjustments. This is an efficient 3-day course on how to reduce development time and at the same time improve the quality. For the online course – the three days are spread out on 5 days – with 4 hours per day.

Learn modern and efficient verification methodology, using logging, alert handling, checkers, waiters, BFMs, transactions, constrained random, functional coverage, requiremen coverage, VVCs, scoreboards, models, etc. But even more important, learn how to write good testbenches to achieve a better overview, readability, maintenance, extensibility, simplicity and reuse.

Architecture and Overview are key to all of this, together with easily understandable high level commands (transactions). This course will show you how easy it is to achieve the benefits above – given the right architecture all the way down and a standard set of commands that are understandable “even” for SW, DSP and HW designers.

The course is 50% labs, to allow you to see for your self how easy it is to write and understand a good testbench. The course assumes that you have a normal designer’s understanding of VHDL and preferably some experience with basic verification.

The course teaches good general verification methodology, and in addition you will get a good understanding of UVVM, BFMs, VVCs, Constrained random, Requirement coverage, etc.

See course info ***Here***

See article on how Doulos recommends UVVM for VHDL testbench architecture

See information about the ESA (European Space Agency) UVVM project here.

See paper on UVVM from DATE 2019, Open source workshop here.

The course is arranged in cooperation with multiple partners around Europe. Please follow their instructions if you have received an email from them.

Live Online

The presentations will be live, and all the participants will have an open audio line in during the course – just as in a normal classrom course. (You can of course mute your self when you are not talking ;-).

The course will be 8:30-12:30 CEST every day. That should hopefully also fit designers from other not too far off time zones.