Very structured testbench infrastructure and architecture
Significantly improves Verification efficiency
Assures a far better Design Quality
The much simpler VHDL variant of UVM
One of the fastest growing FPGA verification methodologies worldwide
UVVM is your best VHDL Verification Methodology today - and is being continuously improved
EmLogic has continued the Bitvis legacy and has been architecting and leading the development on the UVVM methodology and library since the termination of Bitvis. (more on EmLogic’s Bitvis legacy)
10 March 2026: FPGA Meetup in Bergen @HVL: 1) Assertions 2) Requirements Tracking
17 March 2026: EIF Seminar, Trondheim; ‘FPGA forklart for software-utviklere, og FPGA i et KI-perspektiv’
24 March 2026: Guest lecture at NTNU, Trondheim
21 May 2026: Webinar via Aldec: ‘Simple Testbench step-by-step, Part 1’
4 June 2026: Webinar via Aldec: ‘Simple Testbench step-by-step, Part 2 – including a demo’
30 June, 1 July 2026: FPGA Conference (Munich, DE): a) ‘UVVM : The UVM for VHDL – only simpler’ b) ‘Assertions in VHDL and UVVM, Plus the newest features of UVVM’ c) Tutorial: ‘The inside of a good VHDL Verification Component‘ d) Tutorial: ‘Enhanced Randomisation and Functional Coverage, including the latest Questa UVVM extensions’
8 September 2026: FPGAworld, Stockholm: ‘The UVM for VHDL – only simpler’
6 October 2026: FPGA Horizons, London: ‘Get the right FPGA quality through efficient Requirements tracking’
