Very structured testbench infrastructure and architecture
Significantly improves Verification efficiency
Assures a far better Design Quality
The much simpler VHDL variant of UVM
World-wide #1
VHDL Verification Methodology
UVVM is your best VHDL Verification Methodology today - and is being continuously improved
EmLogic has continued the Bitvis legacy and has been architecting and leading the development on the UVVM methodology and library since the termination of Bitvis. (more on EmLogic’s Bitvis legacy)
See our courses on UVVM : ‘Advanced VHDL Verification – Made simple’
Planned presentations++ on UVVM (or related), by EmLogic, in the near future
5 February 2024: Norsk mikrosatellittkonferanse: ‘Critical for space and satellites: FPGA – The What, Why and How’
15 February 2024: FPGA-forum: ‘Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage)’
22 February 2024: Guest lecture at NTNU, Trondheim:
1) Bugs and problems – Worst disasters 2) Developing an FPGA module with a strong focus on efficiency, quality and modifiability
9 April 2024: DVClub (UK): ‘Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage)‘