Very structured testbench infrastructure and architecture
Significantly improves Verification efficiency
Assures a far better Design Quality
The much simpler VHDL variant of UVM
World-wide #1
VHDL Verification Methodology
UVVM is your best VHDL Verification Methodology today - and is being continuously improved
EmLogic has continued the Bitvis legacy and has been architecting and leading the development on the UVVM methodology and library since the termination of Bitvis. (more on EmLogic’s Bitvis legacy)
See our courses on UVVM : ‘Advanced VHDL Verification – Made simple’
Planned presentations++ on UVVM (or related), by EmLogic, in the near future
15 March 2023: ESA’s SEFUW conf. (ESTEC @ Noordwijk, The Netherlands): ‘UVVM: A game changer for efficient FPGA verification and good FPGA quality’
27 March 2023: Guest lecture at University of Oslo:
1) The good, the bad and the ugly 2) Design, verification and some general views on becoming a good FPGA or ASIC developer.
27 March 2023: FPGA design and Verification course for NTNU’s Propulse and Orbit, Trondheim
20 April 2023: Guest lecture at NTNU, Trondheim: 1) Bugs and problems – Worst disasters 2) Developing an FPGA module with a strong focus on efficiency, quality and modifiability
22 June 2023: Verification Futures (Reading, UK): ‘Speed up VHDL verification significantly by making a better testbench architecture and a simpler test sequencer‘
4, 5 July 2023: FPGA Conference (Munich, DE): 1. Presentation: Good FPGA quality through efficient Verification – for beginners 2. Presentation: Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage) 3. Demo: Making a structured VHDL testbench – for beginners 4: Demo: Making a medium advanced testbench using verification components and high-level transactions, with a focus on ensuring proper Specification Coverage
12 September 2023: FPGAworld (Stockholm, SE) ‘Demo: Making a simple but structured VHDL testbench – for beginners’
26 September 2023: FPGA Verification day 2923, (Live online) 1. ‘Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage)’ 2. ‘Demonstrated step-by-step tutorial on making a testbench for proper Specification Coverage (aka Requirement Coverage)’