FPGA & ASIC

The really important factors for High Quality and Fast Development

Some development aspects are far more important than anything else when developing an FPGA or an ASIC. In fact, – if these aspects are not handled properly you risk a significant quality and efficiency penalty.

Lots of problems can easily result in 20 – 30% additional development time and a few more iterations in the lab, but if you don’t handle the critical aspects properly, you could risk spending 2 times or even 3 times the expected FPGA development time, have an unstable product, and waste a lot of time for HW and SW designers as well.

This is why we have made dedicated courses for both Design and Verification, and run these internally for new designers – as well as repeating the most important and complex issues from time to time. 

Design Architecture

A good architecture all the way down leads to much faster and safer design. As a bonus you get a smaller and less power consuming design that is also faster and easier to verify.

Design & Specification coverage

Code coverage, Functional coverage and Specification coverage are all important for good quality, but covering Design Corner cases is also critically important.

Digital Design Pitfalls

FPGA design is Digital Design and not software programming. It is critically important with a deep understanding of Resets, Clocks, Clock domain crossing and the FPGA architecture.

Verification Architecture & Test Sequencer simplicity

A good testbench architecture is almost as important for verification as it is for Design, and easily understandable test sequencers are critical. UVVM is a great starting point.

The mission is to help our customers

Our flexiblity allow us to take on:

  • Any assignment size (One day to several man-years)
  • Complete FPGA or just a module
  • Design, Verification, or both
  • Complete project or a part of your team
  • Walkthrough and Review
  • Tech lead or Project manager
  • Mentor or sparring partner is also an option

FPGA Technology Providers

We have experience with most FPGA technology providers, and we can also recommend technologies based on your needs. We have a huge competence on FPGA design – with lots of really experienced designers.

Design and Verification Languages

VHDL is used 50% world-wide and around 90% in Europe for FPGA develoment. This is why we invest quite a bit of time in methodology and tools for VHDL design and verification. 
We also have experience with Verilog and SystemVerilog, which is typically used for ASIC design. ASIC verification is more mature and standardised - typically using UVM.

Simulation and Verification

For FPGA VHDL verification, we use UVVM which is now the world’s number one VHDL verification methodology. UVVM is free and open source and tool agnostic. It will run on any simulator supporting VHDL 2008. UVVM was in fact created and architected by us. We work closely with both Siemens/Mentor and Aldec - with webinars and integration of UVVM into their tools.

Some of the things we can help you with

Development aspects

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Preparations and Support

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General improvements

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Lorem ipsum dolor sit amet, consectetur adipiscing elit. Tincidunt fames diam metus integer pulvinar non, mauris quisque. Volutpat elit vitae praesent sed nulla quis ac. Sit ut fames pretium sem metus id ipsum mauris. Feugiat vel in tempor integer. Consequat, ut eu arcu interdum feugiat convallis sed massa.

Lorem ipsum dolor sit amet, consectetur adipiscing elit. Tincidunt fames diam metus integer pulvinar non, mauris quisque. Volutpat elit vitae praesent sed nulla quis ac. Sit ut fames pretium sem metus id ipsum mauris. Feugiat vel in tempor integer. Consequat, ut eu arcu interdum feugiat convallis sed massa.

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