FPGA & ASIC

The really important factors for High Quality and Fast Development

Some aspects are by far more important than anything else when developing an FPGA or an ASIC. In fact, – if these aspects are not handled properly you are not taking about a 30-40% additional development time and a few more iterations in the lab. Then you could actually risk spending 2 times or even 3 times the expected FPGA development time, have an unstable product, and also waste a lot of time for HW and SW designers as well. This is why we have made dedicated courses for both Design and Verification, and will run these internally for new designers – as well as repeating the most important and complex issues from time to time.     

Design Architecture

A good architecture all the way down leads to much faster and safer design. As a bonus you get a smaller and less power consuming design, that is also faster and easier to verify.

Digital Design Pitfalls

FPGA design is Digital Design and not programming. It is critically important with a deep understanding of Resets, Clocks, Clock domain crossing and the FPGA architecture 

Verification Architecture and Test Sequencer simplicity

A good testbench architecture is equally important for verification. Easily understandable test sequencers are critical. UVVM is a great starting point. 

Design & Spec. coverage

Code coverage, Functional coverage and Specification coverage are all important for good quality, but covering Design Corner cases is also critically important. 

We take on any assignment for our customers: From small to large, from simple to complex, for any or all development phases. 
Additionally we can help our customers with sparring, walkthrough and review on both development and methodology.

Below are some of the areas we cover. Get in touch if you need our services within FPGA or ASIC

FPGA Technology Providers

We have experience with most FPGA technology providers, and we can also recommend technologies based on your needs. 
We have a huge competence on FPGA design – with lots of really experienced designers.

Simulation and Verification

Our verification implementation is tool agnostic, which means it is 100% portable between the various Tool providers.
For FPGA VHDL we use UVVM, which is initiated and architected by us. UVVM is also tool independent.

Design, Verification & Scripting Languages

Our main development language is VHDL, which is used 50% world-wide and 80-90% in Europe for FPGA design.
We also have experience with Verilog and SystemVerilog, which is typically used for ASIC design.
Python is used for scripting and also for making some of the tools we use.