Courses

The same Author, Presenter and UVVM architect

EmLogic is continuing the courses on FPGA and Verification previously presented by Bitvis

Upcoming courses

VHDL Verification

Advanced VHDL Verification - Made simple

Course Info

  • Location: Munich, Germany
  • Date: 26. - 28. October
  • Time of day: 09:00 - 17:00
  • Temporary registration deadline: 30. September
  • Registration fee: 1850 € *
  • *   +VAT in Germany and some countries
  • For more info on this course, go to course registration
Course registration
FPGA & ASIC Design

Accelerating FPGA and Digital ASIC Design

Course Info

  • Classroom in Munich, Germany
  • 10. - 11. November 2021
  • 09:00 - 17:00
  • Temporary registration deadline: 20. October
  • Registration fee: 1250 € *
  • *   +VAT in Germany and some countries
  • For more info on this course, go to course registration
Course registration

We provide courses on demand

We do both on-site and public courses (Verification, Design or both) worldwide on request. Given sufficient demand - we could arrange courses anywhere