Courses

The same Author, Presenter and UVVM architect as always

EmLogic is continuing the courses on FPGA Design and Verification previously presented by Bitvis. Still Espen Tallaksen - but from a new company - as Bitvis no longer exists.

Upcoming courses

Advanced VHDL Verification - Made simple

Course Info

  • Location: Live online
  • Date: 24 - 28 January 2022
  • Time of day: 08:30 - 13:00 CET
  • Registration deadline: 10. January
  • Registration fee: 1850 € *
  • *   +VAT in Germany and some other countries
  • For more info on this course, go to course registration
Registration

Accelerating FPGA and Digital ASIC Design

Course Info

  • Location: Live online
  • 8. - 11. November 2021
  • Time of day: 08:30 - 12:30 CET
  • Registration deadline: 4. November
  • Registration fee: 1250 € *
  • *   +VAT in Germany and some othercountries
  • For more info on this course, go to course registration
Registration
VHDL Verification

Advanced VHDL Verification - Made simple

Course Info

  • Location: Live online
  • Date: 24 - 28 January 2022
  • Time of day: 08:30 - 13:00 CET
  • Registration deadline: 10. January
  • Registration fee: 1850 € *
  • *   +VAT in Germany and some other countries
  • For more info on this course, go to course registration
Course registration
FPGA & ASIC Design

Accelerating FPGA and Digital ASIC Design

Course Info

  • Location: Live online
  • 8. - 11. November 2021
  • Time of day: 08:30 - 12:30 CET
  • Registration deadline: 4. November
  • Registration fee: 1250 € *
  • *   +VAT in Germany and some othercountries
  • For more info on this course, go to course registration
Course registration

We provide courses on demand

We do both on-site and public courses (Verification, Design or both) worldwide on request. Given sufficient demand - we could arrange courses anywhere