EmLogic has been invited to DVClub Europe to present UVVM. We see this as a great opportunity to make even more FPGA and ASIC designers aware of UVVM – the worlds’s #1 VHDL verification methodology. We will explain what UVVM is, why it is better than UVM for VHDL designers, and of course what it […]
Eidel implementerer avansert kommunikasjonsprotokoll for space, og EmLogic hjelper til med FPGA-utviklingen. Sjekk artikkel om dette i Elektronikk.