EmLogic is again invited by Siemens EDA to present in their Webinar series ‘FPGA Verification made modern’. We appreciate the cooperation with Siemens EDA and see this as a great opportunity to make even more FPGA and ASIC designers aware of UVVM – the world’s #1 VHDL verification methodology.
You can register for the event at Siemens EDA
Check out more info on UVVM
Abstract for this presentation:
The UVVM (Universal VHDL Verification Methodology) is the fastest growing FPGA verification methodology – independent of language, and number 1 for VHDL. This is due to the improvement UVVM yields in both FPGA quality and development time.
This open-source Library and Methodology has the most extensive VHDL verification support available and lets you verify really complex DUTs in a very efficient manner providing modularity, reusability, constrained-random stimulus and functional coverage similar to UVM, but all in a way familiar to VHDL designers. UVVM also has the largest library of open source VHDL verification models and components. With more than 50% of all FPGA designers using VHDL, UVVM provides a great verification solution for these users.
This presentation will provide an introduction to UVVM and get you started using UVVM on your next (or current) project.