EmLogic and UVVM in Electronic Engineering Journal

Meet UVVM: The World’s #1 VHDL Verification Methodology That’s the heading of the article in EEJournal, written by the international guru Clive “Max” Maxfield. “I’m happy (albeit puzzled) to tell you that things seem to be getting better with respect to verifying FPGA, ASIC, and system-on-chip (SoC) designs. The reason I say this is that […]