EmLogic is again one of the main contributors to ‘FPGA Conference Europe’ in July – with two presentations and two tutorials.
On Tuesday two presentations:
- Good FPGA quality through efficient Verification – for beginners
- Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage)
Then on Wednesday two tutorials:
- Making a structured VHDL testbench – for beginners
- Making a medium advanced testbench using verification components and high-level transactions, with a focus on ensuring proper Specification Coverage
We see this as a great opportunity to make even more FPGA and ASIC designers aware of UVVM – the fastest growing FPGA verification methodology over the last 4 years.
Check out the event information including abstracts for all our presentations and tutorials.
Check out UVVM