FPGA Meetup and Guest lectures in Bergen, 17 October

In cooperation with “Bergen FPGA Gruppe”, University of Bergen and Western Norway University of Applied Sciences (Høgskulen på Vestlandet), we will run two sessions on FPGA Design and Verification as shown below. The first session is targeted at FPGA developers in the industry, and the last session on students and academia, but both sessions are of course open to all.

Location: Høgskulen på Vestlandet, Rom E121.  https://lnkd.in/dzHvymmM

Bergen FPGA group


Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage)

Specification coverage is getting more and more attention, and is critical for safety (e.g. DO-254) and mission critical (e.g. ESA space) applications. Unfortunately, this is often handled manually, which is really time-consuming and error-prone. UVVM’s Specification coverage allows a very efficient collection of predefined requirements, and it generates the reports you need for both mission-critical and safety projects, and in fact for any project where quality is important.

This presentation gives a brief overview of Specification Coverage before going into more details of proper Requirements Tracking. It also shows what is provided with UVVM and how this could be applied. UVVM is free and Open Source, and so are all the interface models, randomisation, functional coverage and specification coverage.

Enhanced Randomisation and Functional Coverage – and how this will help you make better VHDL testbenches 

UVVM published new functionality for Advanced and Optimised Randomisation and Functional Coverage in October 2021 as a part of the ESA (European Space Agency) UVVM project. This release takes understanding and readability of these features to a new level and also introduces functionality not previously available for VHDL testbenches. The user threshold is far lower than SystemVerilog and makes it easy for VHDL designers to use this advanced functionality. The randomisation and coverage functionality in UVVM may of course be integrated with any other VHDL verification methodology.

This presentation will explain all of this and also discuss the use of Randomisation and Functional Coverage in general.

Guest lectures

This could also be very interesting for the industry

The good the bad and the ugly (45 min) 

The way you implement your FPGA design and write your code has a huge impact on your development efficiency and product quality. The strange thing is that even many experienced designers tend to write both bad and ugly code. Does it matter if the code is ugly if it works in the lab? Yes – definitely, and for several reasons. First of all, – the probability that ugly code has serious bugs is far higher than for good code. Also, any change made to ugly code has a far higher risk of introducing bugs. And of course – ugly code makes it far more difficult to do a proper review. More time consuming, often frustrating, and with a far worse review quality. Bad and ugly code often results in errors that may be difficult to find and terrible to correct. This presentation will show some examples of bad and ugly code, how they result in inefficiency or bugs, and also suggest some remedies and suggestions for improvements – in order to write good code. (Examples will be in VHDL, but apply equally well for other languages).”


Demo: Making a simple but structured VHDL testbench – for beginners (60 min)

This step-by-step demo is intended for designers and verification engineers who want to learn how to make better and more structured VHDL testbenches.

This session will show you what is needed for *any* good testbench, independent of complexity. 

We will make a testbench from scratch for a simple VHDL module and do the following – using well documented VHDL procedures and functions from UVVM, an open source VHDL verification methodology, growing faster than any other FPGA verification methodology.

  • Add a balanced and controllable clock generator
  • Add logging of progress in a simple way
  • Check default values and reset
  • Access module via an interface – using BFMs (Bus Functional models)
  • Check output signals with and without a positive acknowledge
  • Wait for flag or interrupt or a given value – with a timeout
  • Check that signals have been stable – without pulses or spikes for a given time
  • Change verbosity to show different groups of messages in the transcript
  • Report an alert summary
  • … and more

The presented solution is using UVVM Utility Library and BFMs (also Open source), but the principles and mechanisms are 100% state of the art general verification methodology – independent of library.

Although this testbench is applied on a very simple DUT (Device Under Test), the same principles apply also to advanced testbenches for complex DUTs. (But the advanced testbenches need more on top.)