Jan:   Course: ‘Advanced VHDL Verification – Made simple’  (International)
Mar:   DVCon US: ‘UVVM – Bringing UVM to VHDL’
Mar:   Guest lectures in Bergen (UiB/HVL): One on FPGA design and one on verification
Mar:   Siemens EDA, Verif. Horizons: ‘UVVM – VHDL verif. meth. for faster & better FPGA & ASIC Verif.’
Apr:   Guest lectures in Oslo (UiO): One on FPGA design and one on general FPGA issues 
Apr:   Webinar via Aldec: ‘FPGA Design Architecture – The main key to both quality and efficiency’
May:  Webinar via Aldec: ‘The key to checking the design quality in an efficient and reusable manner’
May:  Webinar via Aldec: ‘Randomization – The Why, When, What & How for FPGA verification’
May:  Webinar via Aldec: ‘Code Coverage, Functional Cov. and Specification Cov. for FPGA Verification’
May:  ESA:  Final presentations (for the 2nd UVVM project)
Jun:   Verification Futures Conf. (UK): ‘The lack of an important verification knowledge’
Jun:   Space meet-up (Kjeller): ‘FPGA – What, why and how to get there?’
Jun:   Siemens EDA, Learning platform: ‘Introduction to UVVM’
Jun:   DVClub (UK), ‘UVVM – UVM for VHDL designers, – An introduction’
Jul:    FPGA conference Europe (Munich): 
           a) ‘UVVM – An introduction to the world’s #1 VHDL verification methodology’
           b) ‘UVVM Enhanced Randomisation and Functional Coverage. Make better VHDL testbenches’
           c) Lab: ‘Making a structured VHDL testbench – for beginners ‘
           d) Lab: ‘Making an advanced TB using models, scoreboards, VVCs, high-level transactions, …’
Aug:  Siemens EDA, FPGA verif. made modern: ‘UVVM – The UVM for VHDL – only simpler’
Sep:   FPGA-forum (Trondheim): ‘Functional Safety on FPGA’
Sep:   FPGA-forum (Trondheim): ‘Enhanced Randomisation and Functional Coverage’
Sep:  Siemens EDA, Partner blogs: ‘FPGA and ASIC development rely on overview and readability‘
Sep:   FPGAworld (Stockholm): ‘Constr. Rand. & Funct. Cov. for VHDL verif, – understandable for anyone’
Sep:   Webinar via Electra IC (Turkey): ‘UVVM – UVM for VHDL designers – An introduction’
Sep:   TWEPP CERN-conf (Bergen): ‘UVVM – Worldwide #1 for VHDL verification Made in Norway’
Sep:   Siemens EDA / Trias, Verification Day: ‘VHDL Testbench Randomisation – Great for better Quality’
Oct:   Guest lectures in Trondheim (NTNU): One on FPGA design and one on verification
Oct:   Spaceport Norway (Oslo): ‘Norwegian IP in cooperation with ESA – Now used world wide’
Nov:  Course: ‘Accelerating FPGA and Digital ASIC Design‘  (International)
Nov:  Course: ‘Advanced VHDL Verification – Made simple’  (International)