Universal VHDL Verification Methodology

UVVM is an Open Source VHDL testbench infrastructure, Architecture, Library and Methodology for making better VHDL tesbenches. UVVM is used world wide to speed up verification and improve the overall FPGA design quality. Applicable for both FPGAs and ASICs.

Utility Library - Verification entry level

Almost all testbenches should be self-checking and have the following minimum functionality:

 

  • Logging and verbosity control - to allow good progress reports and simpler debugging
  • Alert handling – to clearly show exceptions, count them and allow various actions
  • Extended string handling – to make it easier to make good log and alert messages
  • Simple randomisation – because this often detects problems you didn’t think of
  • Value Checkers – as checking signal outputs is a major activity in any testbench
  • Signal Expectors – as you are very often waiting for a signal (e.g. an interrupt)
  • Stability checkers – as you must make sure there has been no activity or spike on a given signal 


In addition to various support to make it easier to make good BFMs (Bus Functional Models) 
All of this helps you make a better testbench faster, and improves overview, readability, maintainability, and reuse.

Lorem ipsum dolor sit amet, consectetur adipiscing elit. Tincidunt fames diam metus integer pulvinar non, mauris quisque. Volutpat elit vitae praesent sed nulla quis ac. Sit ut fames pretium sem metus id ipsum mauris. Feugiat vel in tempor integer. Consequat, ut eu arcu interdum feugiat convallis sed massa.

Lorem ipsum dolor sit amet, consectetur adipiscing

Lorem ipsum dolor sit amet, consectetur adipiscing elit. Vitae bibendum enim, ullamcorper consectetur metus sapien consectetur quis. Molestie amet turpis felis sit nunc enim platea faucibus. Enim vulputate suspendisse nec porta massa diam. Lobortis etiam egestas diam, ornare sed.

Advanced verification framework

Almost all testbenches should be self-checking and have the following minimum functionality:

 

  • Logging and verbosity control - to allow good progress reports and simpler debugging
  • Alert handling – to clearly show exceptions, count them and allow various actions
  • Extended string handling – to make it easier to make good log and alert messages
  • Simple randomisation – because this often detects problems you didn’t think of
  • Value Checkers – as checking signal outputs is a major activity in any testbench
  • Signal Expectors – as you are very often waiting for a signal (e.g. an interrupt)
  • Stability checkers – as you must make sure there has been no activity or spike on a given signal 


In addition to various support to make it easier to make good BFMs (Bus Functional Models) 
All of this helps you make a better testbench faster, and improves overview, readability, maintainability, and reuse.

Lorem ipsum dolor sit amet, consectetur adipiscing elit. Tincidunt fames diam metus integer pulvinar non, mauris quisque. Volutpat elit vitae praesent sed nulla quis ac. Sit ut fames pretium sem metus id ipsum mauris. Feugiat vel in tempor integer. Consequat, ut eu arcu interdum feugiat convallis sed massa.