As you can see in the example code, the UVVM Assertion keeps the abstraction of the assertion high, while still giving us room to control enabling/disabling of the configuration, as is common in a process containing native VHDL assertions. We have chosen longer descriptive names for the more complex assertions, since they would commonly only be instantiated once, as opposed to UVVM utility checkers, which will often be called many times in the sequencer.
We hope that by using UVVM, you will make your verification more readable, easier to maintain, and easier to modify when needed. The goal of introducing UVVM Assertions as part of UVVM was to add one-line assertions that can be run concurrently while you execute a normal sequential verification. We have opted to be inspired by Accelleras’ OVL list of assertions, and if you are already using OVL, the UVVM Assertions wiki includes comparative assertions that cover the same properties. We hope you will find the use for and try out UVVM Assertions in your next verification setup! Don’t hesitate to reach out to us if you have any issues or need guidance on using UVVM.