FPGA - EmLogic AS

FPGA & ASIC

EmLogic is the leading FPGA Design centre in Norway and Scandinavia

Bold claim?

We do both FPGA and Digital ASIC development for customers. From a Digital Design and Verification point of view, there is not much difference between FPGA and ASIC for front-end design.

We aim to excel at all the important aspects of FPGA and ASIC design.

The really important factors for High Quality and Fast Development

Some development aspects are far more important than anything else when developing an FPGA or an ASIC. In fact, – if these aspects are not handled properly you risk a significant quality and efficiency penalty.

Lots of problems can easily result in 20 – 30% additional development time and a few more iterations in the lab, but if you don’t handle the critical aspects properly, you could risk spending 2 times or even 3 times the expected FPGA development time, have an unstable product, and waste a lot of time for HW and SW designers as well.

This is why we have made dedicated courses for both Design and Verification, and run these internally for new designers – as well as repeating the most important and complex issues from time to time.

Design Architecture

A good architecture all the way down leads to much faster and safer design. As a bonus you get a smaller and less power consuming design that is also faster and easier to verify.

Design & Specification coverage

Code coverage, Functional coverage and Specification coverage are all important for good quality, but covering Design Corner cases is also critically important.

Digital Design Pitfalls

FPGA design is Digital Design and not software programming. It is critically important with a deep understanding of Resets, Clocks, Clock domain crossing and the FPGA architecture.

Verification Architecture & Test Sequencer simplicity

A good testbench architecture is almost as important for verification as it is for Design, and easily understandable test sequencers are critical. UVVM is a great starting point.

The mission is to help our customers

Our flexibility allow us to take on:

Any assignment size, from one day to several years
Complete FPGA or just a module
Design, Verification, or both
Complete project or a part of your team
Walkthrough and Review
Tech lead or Project manager
Mentor or sparring partner is also an option

VHDL Conventions

VHDL conventions are essential guidelines that improve the clarity, consistency, and quality of hardware description code. By following these best practices, developers can write code that is easier to read, maintain, and scale.

At EmLogic, we emphasize robust architecture and solid methodologies to ensure efficient and reliable hardware design. Adopting these conventions helps us maintain high standards, streamline development processes, and enhance collaboration across projects.

VHDL Conventions

FPGA Technology Providers

We have experience with most FPGA technology providers, and we can also recommend technologies based on your needs. We have a huge competence on FPGA design – with lots of really experienced designers.

Design and Verification Languages

VHDL is used 50% world-wide and around 90% in Europe for FPGA develoment. This is why we invest quite a bit of time in methodology and tools for VHDL design and verification. We also have experience with Verilog and SystemVerilog, which is typically used for ASIC design. ASIC verification is more mature and standardised - typically using UVM.

Simulation and Verification

For FPGA VHDL verification, we use UVVM which is now the world’s number one VHDL verification methodology. UVVM is free and open source and tool agnostic. It will run on any simulator supporting VHDL 2008. UVVM was in fact created and architected by us. We work closely with both Siemens/Mentor and Aldec - with webinars and integration of UVVM into their tools.

Things we can help with

General improvements

Digital Design Course

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Verification Course

Methodology & Development process

Competence improvement

Reuse and Design for Reuse

IP development

Development aspects

Design and Architecture

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Verification and Architecture

High Level Design

System-on-Chip (SoC/SoPC)

Synthesis + P&R

Low power design

Safety and Mission criticals

UVVM

Security

Signal processing

Pitfall prevention

Resource optimalisation

Scripting

Integration/lab test

Preparations and Support

Concept and Feasibility

Specification

Technology evaluation

Risk Analysis and Planning

Sparring partner

Walkthrough and Review

Verification/test plan

HW - FPGA integration

SW - FPGA integration

Regression testing

FPGA Posts

FPGA & ASIC

EmLogic is the leading FPGA Design centre in Norway and Scandinavia

The really important factors for High Quality and Fast Development

Design Architecture

A good architecture all the way down leads to much faster and safer design. As a bonus you get a smaller and less power consuming design that is also faster and easier to verify.

Design & Specification coverage

Code coverage, Functional coverage and Specification coverage are all important for good quality, but covering Design Corner cases is also critically important.

Digital Design Pitfalls

FPGA design is Digital Design and not software programming. It is critically important with a deep understanding of Resets, Clocks, Clock domain crossing and the FPGA architecture.

Verification Architecture & Test Sequencer simplicity

A good testbench architecture is almost as important for verification as it is for Design, and easily understandable test sequencers are critical. UVVM is a great starting point.

The mission is to help our customers

VHDL Conventions

VHDL Conventions

FPGA Technology Providers

We have experience with most FPGA technology providers, and we can also recommend technologies based on your needs. We have a huge competence on FPGA design – with lots of really experienced designers.

Design and Verification Languages

Simulation and Verification

Things we can help with

General improvements

Development aspects

Preparations and Support

FPGA Posts

Bergen: FPGA-meetup & Guest Lecture

Introduction to Scoreboards in UVVM

Using variables as registers in VHDL

Designing FSMs in VHDL

Main office (Legal)

Strøket 3, Asker, Norway

Branch offices

Krambugata 14, Trondheim, Norway

Tordenskiolds gate 2, Oslo, Norway

Org.nr. 926 408 739

Copyright, 2021 EmLogic