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We’re excited to invite you to Høgskulen på Vestlandet (HVL) Kronstad for an inspiring day with a guest lecture by our CEO, Espen Tallaksen, followed by an FPGA meetup featuring engaging presentations and networking.
Full program details are available below, and here on LinkedIn.
This event is open to everyone, and we hope to see you there!
Please send an email to Eivind Vågslid Skjæveland at HVL if you are coming – to assure that we have enough coffee.
09:00-11:00 Guest lecture (Open to anyone)
Making a simple testbench – step-by-step (2 * 45 minutes)
Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. On top of that they take far too much time to implement and provide close to no support when debugging potential problems.
This presentation will show and exemplify how to build a far better testbench with respect to all these issues – in significantly less time. The presentation will also explain how this verification approach even results in reduced design time and reduced debug time. UVVM Utility Library is open source and should really be used by anyone making a VHDL testbench (unless they have a better system available). The library was first time released in April 2013 and is today being used world-wide.
Verification is critical knowledge for an FPGA designer today – and thus very important also for students.
13:00-16:00 FPGA meetup (Open to anyone)
Two presentations followed by social
A: FPGA Design Architecture – The main key to both quality and efficiency
The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and a bad design architecture can be about 50% of the workload and a high degree of detected and undetected bugs. Most design architectures can be improved and optimized to increase both quality and efficiency.
The FPGA design architecture also affects several project and product characteristics such as reusability, power consumption, resource usage, timing closure, clocking issues, implementation clarity, review easiness and verification/test workload
B: A pragmatic approach to improving your FPGA VHDL verification
A good architecture is very important for FPGA design, but it is in fact equally important for verification of complex FPGA design. The verification architecture determines the verification efficiency and the product quality for complex designs.
The difference between a good and a “normal” verification architecture could be many hundred hours, and for medium to complex designs even as much as a couple of thousand hours. The only good thing about this – is that you can easily do something about it. UVVM was made exactly for this and is free and open source – and used by 35-40% of all FPGA VHDL designers world-wide. A new ESA (European Space Agency) project has just been initiated to extend UVVM even further.
In this presentation, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture. We will also discuss the importance of testbench sequencer simplicity and how it can be used to control multiple VHDL Verification Components simultaneously. We will show testbench examples for a simple interrupt controller, for AXI, for Avalon and more – to illustrate how UVVM will help allow pragmatic and simple verification of both simple and complex DUTs.
C: Social
Welcome!
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