Meet UVVM: The World’s #1 VHDL Verification Methodology
That’s the heading of the article in EEJournal, written by the international guru Clive “Max” Maxfield.
“I’m happy (albeit puzzled) to tell you that things seem to be getting better with respect to verifying FPGA, ASIC, and system-on-chip (SoC) designs. The reason I say this is that the last time I turned my attention to this arena, people were saying that the design and verification phases of a complex device consumed 30% and 70% of the total development time, respectively. By comparison, someone recently informed me that these numbers are now more like 50% and 50%, which means either we’ve become better at doing verification or worse at doing design“, Clive writes in his article.
UVVM enables quality and efficiency
“I have to admit that the verification of today’s uber-complex FPGA and ASIC/SoC designs is not my area of expertise, but I’ll try to convey a hint of a sniff of a whiff as to what this is all about. We’ll start with the base/entry level in the form of the Utility Library.”
You can find the whole article by Clive here, and you can read more about UVVM here.
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