EmLogic and UVVM in Electronic Engineering Journal

Meet UVVM: The World’s #1 VHDL Verification Methodology That’s the heading of the article in EEJournal, written by the international guru Clive “Max” Maxfield. “I’m happy (albeit puzzled) to tell you that things seem to be getting better with respect to verifying FPGA, ASIC, and system-on-chip (SoC) designs. The reason I say this is that […]

Free Webinars on FPGA Design and Verification Best Practices

EmLogic held a free webinar with a large international FPGA tool vendor The four parts are independent of each other, but they all contain useful recommendations and hints on how to improve your development flow. Check them out here: FPGA Design/Verification Best-Practices for Quality and Efficiency Part 1: FPGA Design Architecture Optimization FPGA Design/Verification Best-Practices […]

Prehistory

Digitas – the beginning The Design Centre prehistory of EmLogic is important, as it shows our Design Centre background in many ways – through almost 20 years: Our methodology focus Our standing in the Norwegian Electronics Industry Our customer focus and openness Our tools and Open source achievements Our history of courses, presentations and guest lectures Our experience and deep […]