Introduction to Scoreboards in UVVM
The most common kind of verification of a design made in VHDL is simple directed testing where the expected data is expected in the same order as the stimuli th... Read more.
Using variables as registers in VHDL
A register in an FPGA is a storage element that can hold one bit or more. In VHDL there are two methods of inferring registers. The most common method is to use... Read more.
Trondheims office lab
Since its startup in 2021, EmLogic has grown from one employee to over 40 employees in less that three years. Most of these employees are in Asker and Oslo, but... Read more.
Strøket 3, Asker, Norway