I’ve had my eyes on the Cologne Chip GateMate FPGA for a while. A European FPGA embracing the open-source yosys+nextpnr toolchain, more than enough to get me intrigued. After hearing about it on FPGA-forum 2026 in Trondheim, I acquired an Olimex GateMate-A1 EVB and a cheap OV7670 camera module to start putting together a demo. Being the Edge AI enthusiast that I am – and having had way too much fun with the sketch recognition demo I did recently – I decided to do a version of the sketch recognition demo to this board. But this time, with a live video camera view of a sketchpad, and recognizing the sketches with a logic neural network.
Originally founded in 1994 as a pioneer in ISDN ASICs and telecommunications ICs, Germany’s Cologne Chip applied their silicon expertise to enter the programmable logic market in 2020 with the launch of their GateMate FPGA family. The particular Olimex board I got features the GateMate A1, featuring 20480 8-input LUT trees, 1280 Kb of Block RAM, 4 PLLs, and a 5 Gb/s SerDes. Note the wording 8-input LUT trees: these aren’t 8-input LUTs, but rather a flexible tree construction built from 2-input LUTs, as seen in the figure below. The building blocks are called CPEs, or Central (Cologne?) Programming Elements, also featuring other ways of utilizing the LUT tree as well as flip-flops and arithmetic with full adders and 2×2-bit multipliers.
The real game-changer for me is the software ecosystem though: the entire FPGA toolchain is fully open-source and license-free, based on the mature yosys and nextpnr projects maintained by YosysHQ. The entire prebuilt toolchain is under a gigabyte, and running synthesis, place-and-route and bitfile generation for most circuits finishes in tens of seconds. If you are tired of wrestling with slow, multi-tens-of-gigabytes opaque FPGA vendor software, this might be reason enough to give the GateMate a try. Adding the fact that the chip is manufactured by GlobalFoundries in Dresden, this represents a significant leap forward for European tech sovereignty.
The starting point for the demo was the existing OV7670 example from the prjpeppercorn-test-cases repository, which already implements a OV7670-to-VGA pipeline, although not at full 640×480 resolution to save on resources. For this demo, I wanted a binarized image of the sketch to make the classifier NN smaller, so I decided to opt for a different architecture, summarized in the following dataflow diagram.
A summary of the main dataflow and key features:
Note that there is no soft CPU for handling ROI box movement and rendering, class text display or other tasks – all of this is handled by finite state machines and otherwise modules processing streaming data. There is also no true VGA framebuffer, the rendering logic dynamically overlays the ROI box and text display on top of the monochrome pixels coming from the capture buffer.
For the previous sketch recognition demo I had used 4-bit quantized neural networks, but since this was going to be an FPGA demo I wanted to revisit an idea that is increasingly popular for TinyML: logic neural networks (LNNs). Partially pioneered by yours truly back in the day, the concept here is to train the neural network in a very specific way with fan-in-constrained, quantized neurons such that we can pack entire neurons into FPGA LUTs, as illustrated in the figure below taken from the LogicNets paper:
This also implies that once training is finished, we can just export everything to pure RTL in Verilog or VHDL – no specialized AI deployment tooling, interpreters, or runtime wrappers beyond your standard FPGA synthesis flow. No control logic, external memory or multiply-accumulates, as everything turns into a compact, feedforward RTL circuit implementing the complete neural network and performing one inference per clock cycle, with prior work demonstrating throughput up to hundreds of millions of inferences per second. In the past few years, the research frontier around these ideas has been pushed forward quite significantly: we have works like NeuraLUT which pack entire small neural networks into LUTs, application studies ranging from atrial fibrillation detection to keyword spotting, and exploring different ways to set up differentiable relaxation like difflogic and WARP-LUT.
The researchers behind WARP-LUT have also put together torchlogix, an open-source PyTorch-based library for logic neural networks, which became my weapon of choice for this demo. It was very straightforward to port the Brevitas training scripts for the Quick, Draw! sketch dataset to torchlogix, and then it was onwards to exploring architectural alternatives for the demo. As always is the case for TinyML, there are strict accuracy-resource trade-offs to be considered. For this demo, I was looking for a result in the 80%+ accuracy range, and ideally consuming less than one third of the resource on the GateMate FPGA to make room for future expansion. I sampled and evaluated design points from the following part of the design space with the following parameters, training the neural network with torchlogix, exporting to Verilog and then synthesizing with yosys:
synth_gatemate -top circuit -luttree -nomx8 | Convolutional features | Sparse-linear features | Connectivity | LUT rank | Accuracy % | Cells |
|---|---|---|---|---|---|
| 16 | 4000, 4000 | fixed | 2 | 87.49 | 24452 |
| 16, 32 | 4000 | fixed | 2 | 84.41 | 22983 |
| 0 | 4000, 4000 | fixed | 2 | 81.54 | 18735 |
| 0 | 1000 | learnable | 4 | 87.11 | 8449 |
| 0 | 500 | learnable | 4 | 81.82 | 4253 |
| 0 | 1000 | learnable | 2 | 81.76 | 5110 |
There are quite a few points in that design space, the table above is only an excerpt to highlight some of the important trends that I observed:
In the end, I opted for the design point highlighted in bold italic – a single sparse-linear hidden layer of 500 neurons of rank 4 LUT neurons, with learnable connections, yielding an accuracy of almost 82% which was good enough for the demo.
Live video: You can see the demo in action in the short video above, recognizing a live sketch. It is also possible to move the red ROI rectangle and change the threshold level for binarization.
Performance: Although the demo is currently running at 16 FPS because of some configuration issue with the OV7670 camera, the neural network is far from being the bottleneck here. The part of the design running the neural network is clocked at 25 MHz, which can do 25 million sketch classifications per second! What would one do with that many classifications per second, do you ask? One idea would be to run detection and not just classification, operating on the full resolution image to automatically draw bounding boxes instead of specifying a manual ROI.
FPGA resources: Below, you can see a breakdown of post-synthesis resources for the top-5 biggest components. In total, the design uses 13430 cells, which is around one third of the total resources on the GateMate-A1. So plenty of room for more bells and whistles in a more advanced future demo!
| Module | Cells | % of design | ADDF | L2T4 | L2T5 | LUT1 | LUT2 |
| neural network | 4274 | 31.82% | 324 | 1575 | 633 | 129 | 347 |
| ROI capture | 3587 | 26.71% | 186 | 1612 | 744 | 53 | 143 |
| UART control | 1988 | 14.80% | 297 | 229 | 91 | 56 | 76 |
| argmax computation | 1517 | 11.30% | 288 | 206 | 70 | 288 | 59 |
| renderer | 902 | 6.72% | 263 | 192 | 98 | 119 | 83 |
In conclusion, the Cologne Chip GateMate FPGA proves that European tech sovereignty is a highly capable reality, with chips manufactured right in Dresden and empowered by a completely open-source and license-free ecosystem based on yosys and nextpnr. But perhaps the most exciting takeaway is how cutting-edge research in LNNs allows us to train fan-in-constrained, quantized models and export them directly into pure RTL without any external memory or control logic overhead. These techniques make it possible to pack entire neurons into standard LUTs, unlocking blazing fast machine learning performance. Tens of millions of classifications per clock-cycle-driven second while consuming only a tiny fraction of the available FPGA resources! If you want to see what is possible for your Edge AI applications, please feel free to reach out.
Yaman Umuroglu is a Principal Edge AI Designer at EmLogic, where he specializes in deploying highly efficient, specialized machine learning models on FPGAs, microcontrollers, and other resource-constrained devices. He was previously a Principal Engineer at AMD/Xilinx Research working on neural network-hardware co-design for Edge AI on FPGAs.
