Introduction to Scoreboards in UVVM
The most common kind of verification of a design made in VHDL is simple directed testing where the expected data is expected in the same order as the stimuli that produced each output data element. The goal is to verify that some known stimuli towards the DUT results in expected data on the outputs of […]
Using variables as registers in VHDL
A register in an FPGA is a storage element that can hold one bit or more. In VHDL there are two methods of inferring registers. The most common method is to use a signal that updates its value at the rising edge of a clock. The other method is to use a VHDL variable. Both […]
Designing FSMs in VHDL
Introduction Finite State Machines (FSMs) are fundamental building blocks used in digital designs. The FSMs enable designers to encapsulate complex logic into manageable, modular blocks. If it is used in a structured way, the FSM can enhance readability, maintainability, and scalability of digital designs. Among other applications, FSMs are used to control the sequence of […]
FPGA Meetup and Guest lectures in Bergen, 17 October
In cooperation with “Bergen FPGA Gruppe”, University of Bergen and Western Norway University of Applied Sciences (Høgskulen på Vestlandet), we will run two sessions on FPGA Design and Verification as shown below. The first session is targeted at FPGA developers in the industry, and the last session on students and academia, but both sessions are […]
UVVM Specification Coverage
In this article, we delve into the UVVM Specification Coverage VIP, an invaluable toolset that elevates your test benches and tracks compliance to your design requirements. Specification coverage is tremendously useful when also used in combination with say code coverage, in making sure the right test cases are made to properly verify your Device Under […]
EmLogic – a main contributor at FPGA Conference Europe 2023
EmLogic is again one of the main contributors to ‘FPGA Conference Europe’ in July – with two presentations and two tutorials. On Tuesday two presentations: Good FPGA quality through efficient Verification – for beginners Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage) Then on Wednesday two tutorials: Making a structured VHDL […]
Vi søker etter en FPGA / ASIC Designer i Trondheim
Hva kan vi friste med? Ønsker du å bli med på laget hos det ledende FPGA designsenteret i Norge og Norden? Vil du være en del av et raskt voksende miljø og få jobbe med varierte og spennende prosjekter? Vil du bli medeier til en lav kostnad? Vil du jobbe i en bedrift som satser […]
FPGA for Functional Safety Applications
FPGA for Functional Safety Applications Digital safety critical applications are becoming more important as we replace traditional mechanical safety mechanisms with intelligent systems with built in diagnostic capabilities. A major benefit of switching to electronic solutions is to embed diagnostic functionality that would never be possible in pure mechanical solutions. When choosing how to develop […]
EmLogic and UVVM in Electronic Engineering Journal
Meet UVVM: The World’s #1 VHDL Verification Methodology That’s the heading of the article in EEJournal, written by the international guru Clive “Max” Maxfield. “I’m happy (albeit puzzled) to tell you that things seem to be getting better with respect to verifying FPGA, ASIC, and system-on-chip (SoC) designs. The reason I say this is that […]
Presenting UVVM in Siemens’ webinar series 23 August
EmLogic is again invited by Siemens EDA to present in their Webinar series ‘FPGA Verification made modern’. We appreciate the cooperation with Siemens EDA and see this as a great opportunity to make even more FPGA and ASIC designers aware of UVVM – the world’s #1 VHDL verification methodology. You can register for the event […]
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