FPGA for Functional Safety Applications
FPGA for Functional Safety Applications Digital safety critical applications are becoming more important as we replace traditional mechanical safety mechanisms with intelligent systems with built in diagnostic capabilities. A major benefit of switching to electronic solutions is to embed diagnostic functionality that would never be possible in pure mechanical solutions. When choosing how to develop […]
EmLogic and UVVM in Electronic Engineering Journal
Meet UVVM: The World’s #1 VHDL Verification Methodology That’s the heading of the article in EEJournal, written by the international guru Clive “Max” Maxfield. “I’m happy (albeit puzzled) to tell you that things seem to be getting better with respect to verifying FPGA, ASIC, and system-on-chip (SoC) designs. The reason I say this is that […]
Presenting UVVM in Siemens’ webinar series 23 August
EmLogic is again invited by Siemens EDA to present in their Webinar series ‘FPGA Verification made modern’. We appreciate the cooperation with Siemens EDA and see this as a great opportunity to make even more FPGA and ASIC designers aware of UVVM – the world’s #1 VHDL verification methodology. You can register for the event […]
Presenting UVVM at FPGA Conference Europe
EmLogic is one of the main contributors to FPGA Conference Europe this week with two presentations and two labs. One of each for beginners and experience users respectively. We see this as a great opportunity to make even more FPGA and ASIC designers aware of UVVM – the worlds’s #1 VHDL verification methodology. Check out […]
Presenting UVVM for DVClub Europe
EmLogic has been invited to DVClub Europe to present UVVM. We see this as a great opportunity to make even more FPGA and ASIC designers aware of UVVM – the worlds’s #1 VHDL verification methodology. We will explain what UVVM is, why it is better than UVM for VHDL designers, and of course what it […]
Free Webinars on FPGA Design and Verification Best Practices
EmLogic held a free webinar with a large international FPGA tool vendor The four parts are independent of each other, but they all contain useful recommendations and hints on how to improve your development flow. Check them out here: FPGA Design/Verification Best-Practices for Quality and Efficiency Part 1: FPGA Design Architecture Optimization FPGA Design/Verification Best-Practices […]
How to avoid delays in FPGA and ASIC projects
More Efficient and better Quality FPGA and ASIC design with a good Architecture
Live online course: ‘Advanced VHDL Verification – Made simple’ – using UVVM
A general introduction to modern verification methodology and to UVVM – the world-wide #1 FPGA verification methodology, and also the fastest growing verification methodology independent of HDL. Efficiency and quality is all a question of overview, readability, extensibility, maintainability and reuse, – and a good architecture is the answer. This applies for both Design and Verification […]
UVVM to the top in 2020
Fastest growing FPGA verification methodology world-wide We had seen for several years already that UVVM was growing very fast, and all statistics were indicating that UVVM was the fastest growing FPGA verification methodology world-wide, but we had no hard evidence. But then in September, the ‘The 2020 Wilson Research Group Functional Verification Study’ was published […]
We are introdusing EmLogic – the Norwegian FPGA design centre
EmLogic is a high quality Embedded Systems design centre in Norway.