Angle-Of-Arrival
Angle-Of-Arrival – An internal project Keeping track of all the Bluetooth devices that exist today may not seem like an easy task. We use headsets, mobile phones, keyboards and office equipment which all communicate with each other wirelessly. You probably have one or more devices connected at this very moment. What if we could utilize these […]
EmLogic and UVVM in Electronic Engineering Journal
Meet UVVM: The World’s #1 VHDL Verification Methodology That’s the heading of the article in EEJournal, written by the international guru Clive “Max” Maxfield. “I’m happy (albeit puzzled) to tell you that things seem to be getting better with respect to verifying FPGA, ASIC, and system-on-chip (SoC) designs. The reason I say this is that […]
PCB Design Tools
Tools and Methodologies At EmLogic we value great tools and methodologies. Anything that can assist in bringing products to market faster, with a high level of confidence in the technical features, is likely worth the investment needed in tools and training. Cadence Allegro In line with this philosophy, and to support the development of […]
Number representation in Digital Signal Processing
Number representation in Digital Signal Processing Av Espen Flo Eriksen Digital Signal Processing (DSP) systems that perform a specific and continuous processing task are often implemented in FPGA or ASIC technology. Beyond defining the algorithms and functions to be performed, the designer must also select how the numbers in the system are represented. Floating-point representation […]
Presenting UVVM in Siemens’ webinar series 23 August
EmLogic is again invited by Siemens EDA to present in their Webinar series ‘FPGA Verification made modern’. We appreciate the cooperation with Siemens EDA and see this as a great opportunity to make even more FPGA and ASIC designers aware of UVVM – the world’s #1 VHDL verification methodology. You can register for the event […]
Presenting UVVM at FPGA Conference Europe
EmLogic is one of the main contributors to FPGA Conference Europe this week with two presentations and two labs. One of each for beginners and experience users respectively. We see this as a great opportunity to make even more FPGA and ASIC designers aware of UVVM – the worlds’s #1 VHDL verification methodology. Check out […]
Presenting UVVM for DVClub Europe
EmLogic has been invited to DVClub Europe to present UVVM. We see this as a great opportunity to make even more FPGA and ASIC designers aware of UVVM – the worlds’s #1 VHDL verification methodology. We will explain what UVVM is, why it is better than UVM for VHDL designers, and of course what it […]
Samarbeid innen “New Space”
Eidel implementerer avansert kommunikasjonsprotokoll for space, og EmLogic hjelper til med FPGA-utviklingen. Sjekk artikkel om dette i Elektronikk.
Free Webinars on FPGA Design and Verification Best Practices
EmLogic held a free webinar with a large international FPGA tool vendor The four parts are independent of each other, but they all contain useful recommendations and hints on how to improve your development flow. Check them out here: FPGA Design/Verification Best-Practices for Quality and Efficiency Part 1: FPGA Design Architecture Optimization FPGA Design/Verification Best-Practices […]
Elektronikk: EmLogic rendyrker embedded-segmentet
Sjekk artikkel i Elektronikk om EmLogic og UVVM
Strøket 3, Asker, Norway