UVVM is your best VHDL Verification Methodology today - and is being continuously improved
EmLogic has continued the Bitvis legacy and has been architecting and leading the development on the UVVM methodology and library since the termination of Bitvis. (more on EmLogic’s Bitvis legacy)
See our courses on UVVM : ‘Advanced VHDL Verification – Made simple’
Planned presentations++ on UVVM (or related), by EmLogic, in 2025 – and the near future
26 March 2025: ESA’s SEFUW conference: ‘Get the right FPGA quality through efficient verification and Requirements Tracking’
8 April 2025: Guest lecture at UiO, Oslo: 1) The Good, the Bad, and the Ugly 2) Design, Verification and some general views on becoming a good FPGA or ASIC developer
10 April 2025: Guest lecture at NTNU, Trondheim: 1) Bugs and problems – Worst disasters 2) Developing an FPGA module with a strong focus on efficiency, quality and modifiability
8 May 2025: Webinar for Aldec: ‘FPGA Verification with VHDL and UVVM, Part 1: New Features and Best Practices’
21 May 2025: FPGA Developers’ Forum, CERN, Geneva: ‘Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage)’
19 June 2025: Webinar for Aldec: ‘FPGA Verification with VHDL and UVVM, Part 2: Harnessing the Power of VVCs and BFMS‘
1, 2 July 2025: FPGA Conference (Munich, DE): 1. ‘Making simple FPGA testbenches – utilising important quality measures’ 2. ‘FPGA Requirements Tracking and the Requirements Traceability Matrix’ 3: ‘FPGA Verification Architecture – The key to checking the design quality in an efficient and reusable manner’ 4: ‘The important mechanisms to assure a good FPGA quality through efficient simulation’