UVVM is your best VHDL Verification Methodology today - and is being continuously improved
EmLogic has continued the Bitvis legacy and has been architecting and leading the development on the UVVM methodology and library since the termination of Bitvis. (more on EmLogic’s Bitvis legacy)
See our courses on UVVM : ‘Advanced VHDL Verification – Made simple’
Planned presentations++ on UVVM (or related), by EmLogic, in 2024 – the near future
5 February 2024: Norsk mikrosatellittkonferanse: ‘Critical for space and satellites: FPGA – The What, Why and How’
15 February 2024: FPGA-forum: ‘Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage)’
22 February 2024: Guest lecture at NTNU, Trondheim: 1) Bugs and problems – Worst disasters 2) Developing an FPGA module with a strong focus on efficiency, quality and modifiability
9 April 2024: DVClub (UK): ‘Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage)‘
11 April 2024: Webinar for Aldec: ‘Making a structured VHDL testbench, – A Demo for beginners’
7 May 2024: Siemens’ User2User conference (Munich) : ‘Enhanced Randomisation and Functional Coverage – and how this will help you make better VHDL testbenches’
2, 3 July 2024: FPGA Conference (Munich, DE): 1. Presentation: ‘Making a really advanced, but simple-to-understand FPGA testbench for complex DUTs’ 2. Presentatiion/Demo: ‘Verifying a simple DUT (FPGA or module) from scratch with basic verification – for beginners’ 3: Presentation/Demo: ‘Verifying a complex DUT in a simple way from scratch’
10 September 2024: FPGAworld: ‘Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage’